1. Field of the Invention
The present invention generally relates to a semiconductor process. More particularly, the present invention relates to a salicide process.
2. Description of Related Art
Semiconductor device improvements have been largely accomplished by reducing device feature size while predictions for future device sizes do not foresee an end to the trend of ever smaller and denser devices. Reduction in MOS transistor device feature size brings with it reduction in film thickness while the depth of diffusion regions is also reduced. For the salicide process that is used to establish electrical contacts with the active regions, a metal layer is formed over these active regions (the source/drain region and the gate electrode) and subjected to a thermal process.
For several salicide processes, such as titanium and cobalt salicide processes, two thermal processes for annealing are conducted because these metal silicides have two-phase transition temperatures. The two thermal processes cause a first phase transfer during the first thermal process and then the first phase of the metal silicide is changed into a second phase by the second thermal process.
Usually, the first thermal process and the second thermal process are one-step thermal process respectively which are performed from a room temperature to a predetermined temperature. However, the metal silicide formed by the conventional two thermal processes causes rough and non-uniform grains because the metal silicide grains grow so rapidly that junction leakage is easily occurred and metal silicide sheet resistance is deteriorated.